Mitigation of charge sharing in memory devices

Details Mitigation of charge sharing in memory devices Mitigation of charge sharing in memory devices

2008-12-18

2010-12-21

Dinh, Son (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S174000, C365S177000

Reexamination Certificate

active

07855907

ABSTRACT:
One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.

REFERENCES:
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patent: 6545904 (2003-04-01), Tran
patent: 6825077 (2004-11-01), Tran
“Upset Hardened Memory Design for Submicron CMOS Technology”, T. Calin, M. Nicolaidis and R. Velazco, IEEE Transactions on Nuclear Science, vol. 43, No. 6, Dec. 1996, pp. 2874-2878.
“See Analysis and Mitigation for FPGA and Digital ASIC Devices”, Roland Weigand eesa Microelectronics Section, University of Surrey, Dec. 7, 2005, 28 pgs.

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