Misoperation prevention circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307200B, 377 28, H03K 1706, G06F 100, G06F 1100

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active

045188653

ABSTRACT:
A misoperation prevention circuit for preventing the misoperation of the integrated circuit having standby made. The misoperation prevention circuit comprises an integrator for receiving a control signal for controlling the operational mode of the oscillator and first and second gates in the LSI circuit for receiving the output of the integrator, with the output of the first gate being coupled to the oscillator and the output of the second gate being coupled to the internal logic circuit. A first threshold voltage of the first gate is lower than a second threshold voltage of the second gate. The oscillation is triggered when output voltage of the integrator exceeds the first threshold voltage but the internal logic circuits are maintained in a standby mode by the second gate until the output voltage of the integrator exceeds the second threshold voltage. The time between the occurrence of the first threshold voltage and the second threshold voltage is greater than or equal to the time required for the oscillator to reach stable oscillation.

REFERENCES:
patent: 4232236 (1980-11-01), Yomogida et al.
Electronic Engineering, "Power-On Reset/Run Circuits For The CFP1802muP", vol. 51, No. 627, Sep. 1979, pp. 25 and 29.

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