Mismatch detection circuit for duplicated logic units

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307441, G06F 1116

Patent

active

043097685

ABSTRACT:
A detection circuit for detecting a mismatch between the output signals of duplicated logic units (10a, 10b). The output terminals of one of the duplicated logic units are correspondingly connected to the output terminals of the other duplicated logic unit, while the power supply leads of the duplicated logic units (10a, 10b) are connected to a positive voltage source (32) through a current imbalance detector. Any mismatch between the output signals of the duplicated logic units (10a, 10b) will result in the detection of a large imbalance of current being supplied to the duplicated logic units (10a, 10b). Upon detection, the detector will generate an error signal.

REFERENCES:
patent: 2994062 (1961-07-01), Chiapuzio, Jr. et al.
patent: 3078039 (1963-02-01), Anderson
patent: 3337849 (1967-08-01), Lowry
patent: 3471686 (1969-10-01), Connell
patent: 3585377 (1971-06-01), Jessep
patent: 4215340 (1980-07-01), Lejon

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