Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2006-10-24
2006-10-24
Dickey, Thomas L. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S347000, C257SE21564
Reexamination Certificate
active
07126170
ABSTRACT:
A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wherein: the active region is formed, in plan view, to have a body portion and a projecting portion projecting from a periphery of the body portion; the gate is formed, in plan view, to intersect the body portion of the active region, cover a pair of connecting portions connecting a periphery of the projecting portion to the periphery of the body portion and allow a part of the projecting portion to project from a periphery of the gate; and the source region and the drain region are formed in regions of the body portion of the active region which are situated on opposite sides of the gate in plan view, respectively.
REFERENCES:
patent: 6313508 (2001-11-01), Kobayashi
patent: 2001/0015461 (2001-08-01), Ebina
patent: 2001/0028089 (2001-10-01), Adan
patent: 2002/0109187 (2002-08-01), Matsumoto et al.
patent: 1 102 327 (2001-05-01), None
patent: 62-60049 (1987-04-01), None
patent: 2001-168340 (2001-06-01), None
patent: 2001-210831 (2001-08-01), None
patent: 2001-284591 (2001-10-01), None
patent: 2002-246600 (2002-08-01), None
patent: 2002-299633 (2002-10-01), None
English Language Translation of Form 409 Patentability report in PCT/JP2004/000123 (indicating all claims unpatentable).
Iwamatsu, Toshiaki., et al. CAD-Compatible High Speed CMOS/SIMOX Gate Array Using Field-Shield Isolation, IEEE Transactions on Electron Devices, vol. 42, No. 11, Nov. 1995, pp. 1934-1939.
Yeo, Yee-Chia., et al. “Enhanced Performance in Sub-100 nm CMOSFETs using Strained Epitaxial Silicon-Germanium.” 0-7803-6441-4/00/$10.00 © 2000 IEEE, pp. 1-4.
Iwamatsu, Toshiaki., et al. Investigation of Anomalous Leakage Current in Mesa-Isolated SOI MOSFET's, IEEE Electron Device Letters, vol. 18, No. 10, Oct. 1997, pp. 499-502.
Asai Akira
Inoue Akira
Sorada Haruyuki
Takagi Takeshi
LandOfFree
MISFET for reducing leakage current does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MISFET for reducing leakage current, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MISFET for reducing leakage current will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3668791