Misalignment-tolerant methods for fabricating...

Details Misalignment-tolerant methods for fabricating... Misalignment-tolerant methods for fabricating...

2004-04-30

2010-06-01

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C257SE21621, C326S102000, C365S189020, C365S230020

Reexamination Certificate

active

07727820

ABSTRACT:
This disclosure relates to misalignment-tolerant processes for fabricating multiplexing/demultiplexing architectures. One process enables fabricating a multiplexing/demultiplexing architecture at a tolerance greater than a pitch of conductive structures with which the architecture is capable of communicating. Another process can enable creation of address elements and conductive structures having substantially identical widths.

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Gojman, B.; Rachlin, E; Savage, J.E.; “Decoding of Stochastically Assembled Nanoarrays”; VLSI, 2004, Proceedings, IEEE Computer Society Annual Symposium on; Feb. 19-20, 2004; pp. 11-18.
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