MIS-transistor-based nonvolatile memory

Details MIS-transistor-based nonvolatile memory MIS-transistor-based nonvolatile memory

2008-02-25

2009-12-08

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185080, C365S185210

Reexamination Certificate

active

07630247

ABSTRACT:
A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate line, and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the MIS transistors, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output to outside the nonvolatile semiconductor memory device upon power-on thereof.

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