MIS FET and process of fabricating the same

Details MIS FET and process of fabricating the same MIS FET and process of fabricating the same

1987-06-19

1989-10-10

Hille, Rolf

357 233, 357 2311, H01L 2978

Patent

active

048735574

ABSTRACT:
An LDD MIS FET comprises a silicide over the lightly doped regions to reduce the parasitic resistance and to prevent the depletion of the lightly-doped regions, reducing the hot carrier injection effect. By the provision of the silicide, the overall parasitic resistance can be made low. Moreover, the increase in the resistance of the lightly-doped region due to the negative charge being trapped at the interface of or in the oxide film over the lighty-doped region and the resultant degradation in the characteristic are eliminated.

REFERENCES:
patent: 4505024 (1985-03-01), Kawate et al.
patent: 4593454 (1986-06-01), Baudrant et al.
patent: 4698659 (1987-10-01), Mizutani
patent: 4737828 (1988-04-01), Brown
IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 590-596, "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", Tdsng et al.

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