MIS Device employing elemental pnictide or polyphosphide insulat

Details MIS Device employing elemental pnictide or polyphosphide insulat MIS Device employing elemental pnictide or polyphosphide insulat

1983-06-29

1986-01-28

James, Andrew J.

357 2315, 357 232, 357 61, H01L 2934, H01L 2978, H01L 2920, H01L 29161

Patent

active

045675031

ABSTRACT:
Metal-insulator-semiconductor devices are formed on III-V semiconductors utilizing a pnictide rich insulating layer. The layer may be applied by vacuum evaporation, sputtering, chemical vapor deposition, and from a liquid melt. Gallium arsenide, indium phosphide, and gallium phosphide substrates are insulated with an alkali metal high pnictide polypnictide, preferably a polyphosphide, having the formula MP.sub.x where x is equal to or greater than 15, including new forms of phosphorus grown in the presence of an alkali metal where x is much greater than 15. A KP.sub.15 layer is preferred. They may also be insulated with a layer of a solid elemental pnictide, namely phosphorus, arsenic, antimony or bismuth applied by one of the above named processes. An elemental phosphorus layer is preferred. A silicon nitride, Si.sub.3 N.sub.4, layer may be added on top of the pnictide layer to increase the breakdown voltage of the insulating layer.

REFERENCES:
patent: 3383567 (1968-05-01), King et al.
patent: 3571673 (1971-03-01), Ovshinsky
patent: 3700978 (1972-10-01), North et al.
patent: 3877060 (1975-04-01), Shono et al.
patent: 4438351 (1984-03-01), Schuermeyer
Journal of Applied Physics, vol. 54, #8, Aug. 83, "Reactively . . . Sputtered AIN Films as Gate Dielectric" by Fathimulla et al.

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