MIS decoder providing non-floating outputs with short access tim

Details MIS decoder providing non-floating outputs with short access tim MIS decoder providing non-floating outputs with short access tim

1976-05-25

1977-12-13

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307215, 307251, 307DIG5, 365150, 365182, 365203, H03K 1908, H03K 1934, G11C 800, G11C 1504

Patent

active

040631184

ABSTRACT:
In a multiplicity of NAND decoders, each comprises a dynamic ratioless circuit including a capacitor to be charged in response to a precharge pulse, an MOS logic circuit for discharging the capacitor by an address pulse in the non-selection mode, and first and second MOSFETs connected in series between a clock pulse terminal and ground. The first MOSFET conducts in response to the terminal voltage of the capacitor to transmit a clock pulse from its drain and supplies an output to a word line. The terminal voltage of the capacitor in one decoder is applied to the gate of the second MOSFET of another decoder and the word line output of the other decoder is grounded even during the discharging period of the capacitor in the non-selection mode of the other decoder, enabling a synchronous supply of the address and the clock pulses.

REFERENCES:
patent: 3702926 (1972-11-01), Picciano et al.
patent: 3778784 (1973-12-01), Karp et al.
patent: 3796893 (1974-03-01), Hoffman et al.
patent: 3906461 (1975-09-01), Cappon
patent: 3906464 (1975-09-01), Lattin
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3962686 (1976-06-01), Matsue et al.
patent: 3980899 (1976-09-01), Shimada et al.
Cox et al., "An FET 4-Phase Dynamic Off-Chip Driver with Polarity Hold", IBM Tech. Discl. Bull.; vol. 17, No. 2, pp. 466-467; 7/1974.

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