MIS controlled gate turn-off thyristor

Details MIS controlled gate turn-off thyristor MIS controlled gate turn-off thyristor

1987-02-13

1988-01-05

Clawson, Jr., Joseph E.

357 234, 357 43, 357 89, 357 91, H01L 2974

Patent

active

047179406

ABSTRACT:
An MIS controlled gate turn-off thyristor includes a pnpn structure comprised of a first emitter layer, a first base layer, a second base layer and a second emitter layer, and a turn-off MIS transistor for short-circuiting the second base layer to the second emitter layer. A low impurity concentration layer is formed on the second base layer and the second emitter layer is so formed that it extends, through the low impurity concentration layer, into the second base layer. The MIS transistor is formed on the surface portion of said low impurity concentration layer.

REFERENCES:
patent: 4062032 (1977-12-01), Neilson
patent: 4177478 (1979-12-01), Senes
patent: 4224634 (1980-09-01), Svedberg
patent: 4291325 (1981-09-01), Sueoka et al.
patent: 4574296 (1986-03-01), Sueoka et al.
patent: 4587713 (1986-05-01), Goodman et al.
IEEE IEDM Tech. Digest (1984), pp. 282-285, V. A. K. Temple.
IEEE IEDM Tech. Digest (1985), pp. 158-161, M. Stoisiek et al.

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