1977-02-23
1979-09-04
Davie, James W.
357 42, 357 52, 357 54, 357 86, H01L 2704
Patent
active
041670183
ABSTRACT:
A MIS capacitance element formed in a semiconductor substrate of p-(or n-) conductivity type comprises an n- (or p-) type well region formed in one principal surface of the semiconductor substrate and a polycrystalline region formed on the surface of the well region through a gate insulator layer. A polar voltage is applied between the well region and the polycrystalline layer so that the well region is forward biased and no carrier channel region is formed in the surface of the well region. The MIS element is particularly suited for use in a complementary MIS IC and provides almost no voltage or field dependency of the capacitance.
REFERENCES:
patent: 3408543 (1968-10-01), Ono et al.
patent: 3890635 (1975-06-01), Engeler
patent: 3953875 (1976-04-01), Cave et al.
patent: 4012764 (1977-03-01), Satonaka
patent: 4019197 (1977-04-01), Lohstroh et al.
M. A. Polinsky, "Structure For Integrating Two Series Connected Diodes in a Reduced Area", RCA Technical Notes No. 742, Jan. 1968.
Narita Kazutaka
Ohba Kenichi
Davie James W.
Hitachi , Ltd.
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