Mirror suppression circuit and receiver using such circuit

Details Mirror suppression circuit and receiver using such circuit Mirror suppression circuit and receiver using such circuit

2007-07-10

2007-07-10

Payne, David C. (Department: 2611)

Pulse or digital communications

Receivers

Interference or noise reduction

Reexamination Certificate

active

10509210

ABSTRACT:
A mirror suppression circuit includes a first quadrature signal path coupled between quadrature signal input and output terminals and an error correction circuit for correction of amplitude and phase errors in a carrier modulated quadrature signal. To obtain a suppression of both amplitude and phase imbalance of the carrier modulated quadrature signal as well as signal amplitude variations, a quadrature output of the error correction circuit is coupled to an error detection circuit. The error detection circuit detects amplitude and phase errors and provides amplitude and phase control signals to the error correction circuit for a negative feed back of the amplitude and phase errors. The amplitude and phase control signals vary with products of components of the quadrature signal and components of a quadrature reference signal.

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