Patent
1989-05-19
1993-09-21
LaRoche, Eugene R.
395275, G06F 300, G06F 1300
Patent
active
052476545
ABSTRACT:
A circuit determines when a given operation has been performed and starts a counter. If a second operation, particularly an operation complementary to the first operation, is initiated before the counter reaches a predetermined value the second operation is held or delayed until the time is elapsed, after which time the second operation completes.
REFERENCES:
patent: 4234920 (1980-11-01), Van Ness et al.
patent: 4414664 (1983-11-01), Greenwood
patent: 4484263 (1984-11-01), Olson et al.
patent: 4485435 (1984-11-01), Sibley
patent: 4600990 (1986-07-01), Gershenson et al.
patent: 4689766 (1987-08-01), Kent
patent: 4742448 (1988-05-01), Sander et al.
patent: 4872107 (1989-10-01), Marple et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 5097413 (1992-03-01), Mensch, Jr.
IBM Technical Disclosure Bulletin, Method of Power On/Off Diskette Controller, vol. 29, No. 4, Sep. 1986, pp. 1723-1724.
IEEE, Micro, Floppy Disk Data Transfer Techniques, Dec. 1983, pp. 17-23.
Driver Schematic of Driver Adaptor, Multi I/O Card User's Manual, DOC:CB009-1.
Multi I/O Card V.2 User's Manual 19.
Hamid Mustafa A.
Thoma, III Roy E.
Compaq Computer Corporation
Glembock Christopher R.
LaRoche Eugene R.
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