Minimum pulse width address transition detection circuit

Details Minimum pulse width address transition detection circuit Minimum pulse width address transition detection circuit

1994-11-14

1996-02-20

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36518908, 327 26, G11C 700

Patent

active

054935385

ABSTRACT:
A latch circuit is set by a detection circuit which detects a difference between inputs. One of the inputs being delayed by a predetermined period of time. The output of the latch circuit is inverted and delayed through a delay circuit and resets the latch circuit.

REFERENCES:
patent: 4843596 (1984-06-01), Miyatake et al.
patent: 4922122 (1990-05-01), Dubujet
patent: 5088858 (1991-04-01), Ikeda
patent: 5124584 (1992-06-01), McClure
patent: 5313436 (1994-05-01), Matsubishi
patent: 5357480 (1994-10-01), Vinal

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