Minimum pin-count multiplexed address/data bus with byte enable

Details Minimum pin-count multiplexed address/data bus with byte enable Minimum pin-count multiplexed address/data bus with byte enable

1991-09-16

1995-01-31

Black, Thomas G.

Boots, shoes, and leggings

395425, 3649256, 3649602, 3642328, 3642329, 364238, 3642513, 364DIG1, G06F 1200, G06F 1576

Patent

active

053865790

ABSTRACT:
A multiplexed address and data bus system provides a minimum pin count with byte enable and burst address counter support. The partitioning of the address bus includes separate byte enables to indicate specifically which bytes of the word are being accessed, and two independent address lines which can function as a counter to support the burst refill. Both block reads or single datum transfers are handled similarly: a single addressing phase with multiple data phases; and all addresses in the memory system; are derived directly from the same pins regardless of whether it is a block read or not. The system allows for low cost packaging while maintaining a variety of system capabilities.

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