Minimum/maximum data detector

Details Minimum/maximum data detector Minimum/maximum data detector

1995-10-25

1998-03-10

Mai, Tan V.

Boots, shoes, and leggings

G06F 700

Patent

active

057269238

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
The present invention relates to a minimum/maximum data detector for rapidly detecting the minimum or the maximum data from a plurality of numeric data.
2. Background Art
Conventionally, the detection of minimum or maximum dam has generally been carried out using a program on a digital signal processor (hereinafter abbreviated as "DSP"). In order to carry out the detection more quickly, a DSP is used which is provided with specific instructions for executing comparisons of numeric data and carrying out data transfer (i.e., conditional transfer) based on the results of the comparison.
FIG. 5 shows a data ALU in a conventional DSP that executes comparison and conditional transfer according to the specific instructions. The data ALU comprises a memory 1 for storing consecutive numeric data; a register 2 for designating the address when reading out the content of memory 1; and a register 3 for storing an address of memory 1, the address designating the minimum or the maximum data. The memory 1 and registers 2 and 3 are connected to a data bus 20. Furthermore, an input terminal of an arithmetic logic unit 4 for executing the comparison, registers 5 and 6 for storing numeric data to be compared, and the output terminal of an accumulator (which can be replaced by another register) 7 are also connected to the data bus 20. The register 5 is connected to another input terminal of the arithmetic logic unit 4. The operation sequences of various functional circuits arc controlled by a control circuit 8 based on the comparison results.
The functional circuits in FIG. 5 can exchange data via a data bus 20 having an arbitrary bit width in response to commands supplied by a program controller furnished in the DSP. The details of the program for detecting the minimum/maximum data utilizing the above-described circuit .Will be described below with the flowchart in FIG. 6. It should be noted that the flowchart in FIG. 6 is not intended to show a strict order of the processes, but is meant to facilitate comprehension of the processes. For example, even if the flowchart indicates that a plurality of steps are executed sequentially, the steps may in fact be executed simultaneously, in a common machine cycle. Therefore, the scope of the processes executed in one machine cycle is also written in the flowchart. Furthermore, data change timings for the various data are shown in FIG. 8.
In FIG. 8, it is assumed that the memory 1 stores numeric data "0.times.0800," "0.times.0200," "0.times.1000" and "0.times.0000" in its addresses "0.times.0000" to "0.times.0003," respectively. The numeric data are read out sequentially and the maximum data "0.times.1000" will finally remain in the accumulator 7.
The details of the flowchart in FIG. 6 will now be described. First, a prespecified initial value is stored in the accumulator 7 (S31). When detecting minimum data, the initial value is preferably the maximum value within the expressible scope of the numeric data. For example, if the numeric data are expressed by "16" bits width two's complement data, the initial value is preferably "0.times.7FFF." In contrast, when detecting maximum data, the initial value is preferably the minimum value within the expressible scope of the numeric data (for example, "0.times.8000"). The following description presumes detection of minimum data.
Next, the top address of the data stored in the memory 1 is stored in the registers 2 and 3 (S32). Next, the number of the numeric data is stored in a loop counter, the counter being furnished in the control circuit 8, for setting the number of repeats when a repeat control is executed (S33). The first numeric datum (i.e., the numeric datum stored in the address shown by the register 2) is stored in the register 5 (S34), and the content of the register 2 is incremented by "1" (S35).
Next, steps S36 to S43 are repeated a number of times corresponding to the number of the numeric data.
In step S36, the content of the register 5 is transferred to the register 6. In step S37, the contents of

REFERENCES:
patent: 4857882 (1989-08-01), Wagner et al.
patent: 5532948 (1996-07-01), Kohno et al.
"DSP56000/DSP56001 Digital Signal Processor User's Manual", Motorola, Inc., 1990.
"TMS320C5x User's Guide", Texas Instruments, Inc., 1991.
"MN1920 series LSI Instruction Manual", Matsushita Electronics Corp., 1992.

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