Minimum gate delay edge counter

Details Minimum gate delay edge counter Minimum gate delay edge counter

2007-03-27

2007-03-27

Callahan, Timothy P. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Pulse counting or dividing chains

C377S119000

Reexamination Certificate

active

10781560

ABSTRACT:
An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycle corresponding to a predetermined odd or even number of input signal edges, with the logic optimized and protected against entry into “stuck” states. A low power, low gate count edge counter is thus implemented with an output signal duty cycle at least as balanced as the input counter duty cycle.

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