Boots – shoes – and leggings
Patent
1989-06-20
1993-10-05
Trans, Vincent N.
Boots, shoes, and leggings
364489, 364488, G06F 1560
Patent
active
052511472
ABSTRACT:
The interconnection costs of electronically linked objects is minimized by the successive partitioning of the initial logic design. The partitioning is based upon the electrical properties of the drivers and loads of the linked objects forming the design. Further, time critical connections are weighted so as to further minimize interconnection cost. A further method refines the result of the successive partitioning by calculating each linked object's contribution to the overall delay of the design. Both the design of device function and timing and the physical realization of the electronically linked objects are solved jointly to make use of the information available from the logical and physical designs.
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"Partitioning and Placement Technique for CMOS Gate Arrays", by G. Odawara et al., IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems. CAD-6, May 1987, No. 3, pp. 355-363.
Digital Equipment Corporation
Trans Vincent N.
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