Minimizing recovery time

Details Minimizing recovery time Minimizing recovery time

2000-09-13

2001-04-24

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

C331S00100A, C331S018000, C331S025000, C327S142000, C327S156000, C327S159000

Reexamination Certificate

active

06222420

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, in general, to integrated circuits and, more particularly, to Phase-Locked Loop (PLL) devices.
BACKGROUND OF THE INVENTION
Communications systems and computer systems have components that operate at different frequencies. Typically, these systems use Phase-Locked Loops (PLLs) for synchronization of their components. A PLL generally includes a phase detector, a loop filter, a Voltage-Controlled Oscillator (VCO), and a loop divider. The phase detector receives a reference clock signal and a loop clock signal and provides a phase detect output signal that indicates the phase difference between the loop clock signal and the reference clock signal. The phase detector provides the phase detect output signal to an input of the loop filter, which in turn provides a filtered signal to the VCO. The filtered signal indicates the length of time that the two clock signals are out of phase. The VCO provides a clock output signal having a desired frequency. The clock output signal is divided by the loop divider to provide the loop clock signal.
In some systems, it is desirable to switch the reference clock signal between one of two clock signals, i.e., a primary clock signal and a backup clock signal. A multiplexer is used to switch between the two clock signals. During normal operation, the primary clock signal serves as the reference clock signal. In the event of a failure of the primary clock signal, the select input of the multiplexer is toggled such that the backup clock signal becomes the reference clock signal. If the primary clock signal and backup clock signal are out of phase, then the PLL changes the frequency of its output signal to regain phase lock to the new reference clock signal, i.e., the backup clock signal.
The switch between the primary clock signal and the backup clock signal is asynchronous. Therefore, the recovery time of the PLL, i.e., the time it takes for the PLL to regain phase lock, is variable and unpredictable. This is not desirable in systems employing multiple PLLs since it can cause a loss of synchronization. The loss of synchronization between components of these systems can lead to race conditions, code execution failure, improper turning on or turning off of buses, etc.
Accordingly, it would be advantageous to have a PLL device and a method for regaining phase lock in a predictable manner. It would be of further advantage to have a PLL device and method that minimizes the amount of time it takes for the PLL device to regain phase lock.


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patent: 6154508 (2000-11-01), Ott

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