Minimizing read disturb in an array flash cell

Details Minimizing read disturb in an array flash cell Minimizing read disturb in an array flash cell

2011-01-04

2011-01-04

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S196000, C365S207000, C365S210100, C365S189090

Reexamination Certificate

active

07864588

ABSTRACT:
A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.

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