Reexamination Certificate
1996-02-21
2001-02-06
An, Meng-Ai T. (Department: 2783)
Reexamination Certificate
active
06183141
ABSTRACT:
TECHNICAL FIELD
The invention relates to the simultaneous command of the control statuses of a plurality of execution units of a programmable processor, on the basis of a program code stored in a program memory, so as in particular to minimize the memory size of the program code.
The invention applies advantageously but not limitingly to hardware architectures dedicated to implementing, relatively regular and repetitive, intensive numerical processing operations, for example in the processing of animated images, in particular in multi-media communication applications.
BACKGROUND
Conventionally the instructions of a programmable processor code the control statuses thereof, these control statuses fixing the operating configurations of the data path.
The global control status of the processor varies in each cycle of the clock signal on the basis of which it is clocked. When the instructions of the program code which are contained in the program memory are intended simultaneously to control the control statuses of several distinct hardware resources, commonly designated under the generic term of execution units, the control status varies locally in each clock cycle as a function of the various execution units. These execution units can for example be arithmetic and logic units, multipliers, adders or even controllable facilities for inter-connecting the previously mentioned elements, such as multiplexers.
Command of all the possible control statuses on the basis of a succession of instruction words each consisting of the control words intended to command respectively, directly and simultaneously, the various execution units, would be possible but would lead to a very considerable size of the program code, and consequently to the use of a large program memory.
SUMMARY
The aim of the invention is to afford a solution to this problem and to minimize the memory size of the program code on the basis of which the control statuses of the execution units are simultaneously controlled, and hence to reduce the amount of hardware for the program memory.
The aim of the invention is also to allow the simultaneous and independent command of all the execution units whilst fully utilizing the useful field of the control words.
The invention therefore proposes a process for the simultaneous command of the control statuses of a plurality of execution units of a programmable processor, in which groups of control words destined for the various units are generated in succession on the basis of a program code stored in a program memory. According to a general characteristic of the invention, a first segment at least of the program code is stored in a first segment of the program memory, comprising a succession of program words including first base words each having a size less than the sum of the respective sizes of the respective group of control words, and second base words fewer in number than that of the first base words. The various program words are extracted sequentially from this first segment of the program memory. A storage facility is provided whose content is updated at least on the basis of each second extracted base word, and certain at least of the various groups of control words are computed sequentially on the basis of the combining according to at least one predetermined logic relation, of the first extracted base words and of the content of the storage facility. The memory size of the program code is thus minimized.
Stated otherwise, the invention provides in particular for structuring the program code into instructions (first base words) and into directives (second base words). Each instruction is then valid for a single clock cycle whilst the content of the storage facility remains valid in general for a longer duration covering several clock cycles, since it is updated by the directives which are fewer in number than the instructions.
In the sense of the present invention, the expression “update” should be interpreted in a very broad sense encompassing in particular a substituting of at least some bits of the content of the storage facility by some bits at least of the relevant directive, or else the modifying of the content of the storage facility by a logic function defined by the directive, for example an inversion of bits.
Each control word assigned to an execution unit is then obtained from the logical combining of an instruction and of the content of the storage facility updated by the directives. Here again, the term “combining” should be taken in a very general sense, including a straightforward juxtaposing of bits and/or a concatenating of bits and/or a true combining according to a logic function of some at least of the bits of the instructions and directives.
The size of the instructions, and advantageously of all the program words of the program code, which is less than the sum of the elementary sizes of the control words required for command of the execution units, as well as a number of directives which is fewer than that of the instructions, thus leading to a “time factoring” of these directives, make it possible to compact the memory size of the program code.
According to a variant of the invention, each first base word of the program code comprises a block of first instruction words (or “instructions”) which are mutually independent and respectively assigned to the plurality of execution units, whilst each second base word represents a second instruction word (or “directive”) assigned to at least one execution unit. The storage facility is subdivided into a plurality of elementary storage facilities assigned respectively to the plurality of execution units, and whose respective contents are respectively updated at least on the basis of the second corresponding instruction words and, according to a second logic relation assigned specifically to each execution unit, certain at least of the control words assigned to this execution unit are computed sequentially on the basis of the first corresponding instruction words and of the content of the elementary storage facility assigned to this execution unit.
Thus in this variant, the first segment of the program memory contains directly the instructions and directives on the basis of which certain at least of the groups of control words destined for the execution units will be computed.
According to another variant of the invention, on the basis of the combining according to a first predetermined logic relation, of each first extracted base word and of the content of the storage facility, there is computed a program sub-word including a block of first instruction words which are mutually independent and respectively assigned to the plurality of execution units, and/or at least one second instruction word assigned to at least one execution unit. A plurality of elementary storage facilities assigned respectively to the plurality of execution units, and whose respective contents are respectively updated at least on the basis of the second corresponding instruction words are furthermore provided and, according to a second logic relation assigned specifically to each execution unit, certain at least of the control words assigned to this execution unit are computed sequentially on the basis of the first corresponding instruction words and of the content of the elementary storage facility assigned to this execution unit.
Stated otherwise, according to this variant there is provided an additional hierarchy within the structure of the program code. More precisely, the process according to the invention makes it possible to extract, from the program memory, instructions and directives “of higher order” (first and second base words) on the basis of which instructions and directives “of lower order” (first and second instruction words) are computed which will themselves lead to the computation of various control words.
The first and second instruction words can be computed simultaneously or sequentially.
In one or the other of the variants, there is advantageously provision, in the presence of a program word (first variant) or of a
Dufal Frederic
Privat Gilles
An Meng-Ai T.
France Telecom
Fulbright & Jaworski L.L.P.
LandOfFree
Minimizing program code storage for performing regular and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Minimizing program code storage for performing regular and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimizing program code storage for performing regular and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2568796