Minimizing non-linearity errors

Details Minimizing non-linearity errors Minimizing non-linearity errors

2011-08-23

2011-08-23

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

External effect

Temperature

Reexamination Certificate

active

08004345

ABSTRACT:
A system and method for minimizing non-linearity errors induced in output drive voltage of a transmitter circuit due to on-chip process, voltage, and temperature (PVT) variations. The system including an oscillator for converting an input reference bias voltage into a clock output signal, where the input reference bias voltage varies in response to PVT variations. Also included is a counter for counting the clock output signal and generating a count value corresponding to the clock output of the oscillator. A comparison module operatively coupled to the counter compares the count value with a pre-simulated count value to generate an error signal. Based on the error signal generated by the comparison module, a correction logic adjusts an output drive signal of the transmitter circuit making it immune to PVT variations.

REFERENCES:
patent: 7812661 (2010-10-01), Wu et al.
patent: 7834705 (2010-11-01), Seo et al.
patent: 2007/0018713 (2007-01-01), Tripathi et al.
Qadeer A. Khan, et al., “Techniques for on-chip process voltage and temperature detection and compensation”, pp. 1-6.

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