Minimizing logic to determine current state in an output encoded

Details Minimizing logic to determine current state in an output encoded Minimizing logic to determine current state in an output encoded

1994-10-19

1996-07-30

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, G06F 300

Patent

active

055420346

ABSTRACT:
Logic to determine the current state of an output encoded finite state machine is minimized. Specifically, in order to generate logic for a finite state machine, input is received from a user. The input specifies states of the finite state machine, transition conditions between states and output values for each state. For example, a graphical user interface is used to receive a graphic portrayal of a state diagram. Logic is generated which implements the finite state machine from the inputs received by the interface means. Particularly, a plurality of flip-flops is generated. A first set of flip-flops is for storing output for the finite state machine. A second set of flip-flops is used, when necessary, with the first set of flip-flops to uniquely identify each state. When output values of the first set of flip-flops uniquely identify each state, the second set of flip-flops is not used (i.e., the second set of flip-flops is the null set). For each state, a combination of a minimum number of the flip-flops from the first set of flip-flops and the second set of flip-flops is detected which uniquely identifies the state.

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Steve Golson, State Machine Design Techniques for Verilog and VHDL, Synopsys Journal of High-Level Design, Sep. 1994, pp. 1-44.

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