Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2008-07-15
2011-11-15
Garbowski, Leigh (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S104000, C716S132000
Reexamination Certificate
active
08060845
ABSTRACT:
A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.
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Herzl Robert D.
Horton Robert S.
Lauricella Kenneth A.
Milton David W.
Ogilvie Clarence R.
Garbowski Leigh
International Business Machines - Corporation
Wood Herron & Evans LLP
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