Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Manufacturing optimizations
Reexamination Certificate
2011-03-15
2011-03-15
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Manufacturing optimizations
C716S056000, C716S100000, C716S132000
Reexamination Certificate
active
07908573
ABSTRACT:
Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the adjusted value for the adjustment variable. In an embodiment, the adjustment is made in dependence upon a pre-calculated “interconnect optimization database” indicating combinations of values for the plurality of variables which have been pre-determined to minimize exposure of interconnect propagation delay to process variations affecting the subject variable. Different databases, or different entries in the same database, can be provided for minimizing exposure of interconnect propagation delay to process variations affecting each subject variable of interest.
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Office Action mailed May 8, 2009 in U.S. Appl. No. 11/767,292.
Response filed Aug. 10, 2009 to Office Action mailed May 8, 2009 in U.S. Appl. No. 11/767,292.
Garbowski Leigh Marie
Haynes Beffel & Wolfeld LLP
Synopsys Inc.
Wolfeld Warren S.
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