Minimizing adjacent wordline disturb in a memory device

Details Minimizing adjacent wordline disturb in a memory device Minimizing adjacent wordline disturb in a memory device

2007-09-18

2007-09-18

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185170, C365S185180, C365S185230, C365S185280

Reexamination Certificate

active

11417574

ABSTRACT:
A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpassdisturb in response to the selected wordline programming voltage.

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