Minimization of FG-FG coupling in flash memory

Details Minimization of FG-FG coupling in flash memory Minimization of FG-FG coupling in flash memory

2006-02-07

2006-02-07

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240, C365S185220

Reexamination Certificate

active

06996004

ABSTRACT:
Multiple passes of the loop of program verify and programming steps are performed for minimizing the effects of FG—FG coupling during programming a flash memory device. In one embodiment of the present invention, for programming a group of at least one flash memory cell of an array, a first pass of program verify and programming steps is performed until each flash memory cell of the group attains a threshold voltage that is at least X % of a program verify level but less than the program verify level. Then, a second pass of program verify and programming steps are performed until each flash memory cell of the group attains substantially the program verify level for the threshold voltage.

REFERENCES:
patent: 6456528 (2002-09-01), Chen
patent: 6542407 (2003-04-01), Chen et al.
patent: 6847553 (2005-01-01), Chen et al.
patent: 2003/0137888 (2003-07-01), Chen et al.
patent: 2003/0214853 (2003-11-01), Hosono et al.
patent: 2005/0024943 (2005-02-01), Chen et al.

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