Minimization of circuit delay and power through transistor sizin

Details Minimization of circuit delay and power through transistor sizin Minimization of circuit delay and power through transistor sizin

1995-05-01

1999-03-09

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364578, G06F 1750

Patent

active

058809678

ABSTRACT:
A method for minimizing signal delay and power consumption is provided. Through combined power simulation and delay analysis, iterative transistor resizing is performed based on a variety of factors including relative delay of associated circuit paths, nodal switching activities and association of transistors in channel-connected sets.

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