Minimal mask process for fabricating a lateral insulated gate se

Details Minimal mask process for fabricating a lateral insulated gate se Minimal mask process for fabricating a lateral insulated gate se

1986-11-26

1988-01-05

Ozaki, George T.

Fishing, trapping, and vermin destroying

437148, H01L 2138, H01L 21425

Patent

active

047176792

ABSTRACT:
An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device.

REFERENCES:
patent: 4199774 (1980-04-01), Plummer
patent: 4300150 (1981-11-01), Colak
patent: 4409606 (1983-11-01), Wagenaar et al.
patent: 4446176 (1984-08-01), Temple
patent: 4532534 (1985-07-01), Ford et al.
General Electric Company, Corporate Research and Development Center Docket RD-16,869, Ser. No. 935,368, filed 11/26/86, titled Insulated Gate Transistor With Vertical Integral Diode and Method of Fabrication, Inventor(s) B. J. Baliga et al.
Article "Analysis of the Lateral Insulated Gate Transistor" by M. R. Simpson, P. A. Gough, F. I. Hshieh and V. Rumennik, published in the Technical Digest of the International Electron Device Meeting, 1985, pp. 740-743.

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