Minimal logic synchronous up/down counter implementations for CM

Details Minimal logic synchronous up/down counter implementations for CM Minimal logic synchronous up/down counter implementations for CM

1983-08-29

1986-09-09

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Pulse counting or dividing chains

Using bistable regenerative trigger circuits

377116, H03K 2304

Patent

active

046113371

ABSTRACT:
A binary up/down counter stage particularly suitable for CMOS implementation. The counter stage includes an exclusive OR gate having a first input for receiving a toggle signal, a flip-flop having a data input coupled to the output of the exclusive OR gate and Q and Q outputs, the Q output of which provides the stage output and a feedback to the second input of the exclusive OR gate, and a multiplexer having first and second inputs coupled to the Q and Q of the flip-flop respectively, the output of the multiplexer being logically ANDED with a toggle-in signal to provide a toggle-out signal for a further counter stage in cascade.

REFERENCES:
patent: 3243600 (1966-03-01), Fatz
patent: 3588475 (1971-06-01), Scott
patent: 4037085 (1977-07-01), Minorikawa
"B-Directional Counter Using a Cyclic Pseudo-Random Number Generator", Electrotechnology, Jan. 1977, pp. 13-14.
Robert Brownstein, "Up-Down Counter Cuts Parts Count", Electronics, Jun. 8, 1978, p. 164.

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