Minimal delay rate-change circuits

Details Minimal delay rate-change circuits Minimal delay rate-change circuits

1979-11-23

1982-02-16

Stewart, David L.

Multiplex communications

Wide area network

Packet switching

370109, H04B 166

Patent

active

043160611

ABSTRACT:
Minimal delay rate-change circuits for transmitting data samples partitioned into blocks comprise an arrangement of storage devices (101 through 105) between input (100) and output (600) with individual storage lengths increasing according to a geometric progression; storage means (106) arranged between input and output to store all but one of the remaining samples unallocated to the storage devices; input clocking means (201 through 207) to route input samples to appropriate storage devices or means; and output clocking means (501 through 507) to gate the accumulated samples to the output. The topological arrangement relies on the ability of a storage device to shift out while the next lower size storage device is being loaded.

REFERENCES:
patent: 3213201 (1965-10-01), Flood
patent: 3781822 (1973-12-01), Ahamed
patent: 3934094 (1976-01-01), Kobayashi
patent: 3975763 (1976-08-01), Kitamura
patent: 4210781 (1980-07-01), Nishimura
The Bell System Technical Journal, Dec. 1971, pp. 3177-3194, "A General Class of Rate Change Circuits."

Affiliated with

Also associated with

Rating

Minimal delay rate-change circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Minimal delay rate-change circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimal delay rate-change circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-943635