Minimal delay conductive lead lines for integrated circuits

Details Minimal delay conductive lead lines for integrated circuits Minimal delay conductive lead lines for integrated circuits

1996-11-26

1998-11-24

Gensler, Paul

Wave transmission lines and networks

Long lines

Strip type

333246, H01P 308

Patent

active

058413332

ABSTRACT:
In accordance with the invention, a conductive lead line extending between a source and a capacitance load has a width w(x) which is a function of the distance x. For many practical applications such as leads for multichip modules, w(x) can be taken as the exponential function of the distance from the load given by the equation below. For many applications w(x) can be adequately approximated by the first three terms of a power series representation: ##EQU1## where W.sub.0 is the width of the lead line at x=0, C.sub.0 is the load capacitance and C.sub.0 is the area capacitance. For VLSI applications w(x) is a friction which can be designated.noteq.E(W.sub.0, C.sub.0, C.sub.p, C.sub.S, x) where C.sub.p is the perimeter capacitance. E(W.sub.0, C.sub.0, C.sub.p, C.sub.S, x) is derived herein. For most practical applications, w(x) can be adequately approximated by the first three terms: ##EQU2## In contrast with optimal-width rectangular wire, the RC Elmore delay of the optimally tapered lead goes to zero as the driver resistance approaches zero.

REFERENCES:
patent: 3323082 (1967-05-01), Kenneally
patent: 3419813 (1968-12-01), Kamnitsis
patent: 4539528 (1985-09-01), Bayraktaroglu et al.
patent: 5656873 (1997-08-01), O'Loughlin et al.

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