Minimal address state in a fine grain multithreaded processor

Details Minimal address state in a fine grain multithreaded processor Minimal address state in a fine grain multithreaded processor

2004-06-30

2008-03-11

Ellis, Richard L. (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

Reexamination Certificate

active

07343474

ABSTRACT:
In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured to maintain a plurality of program counters (PCs), each of which corresponds to one of a plurality of threads that the processor is configured to have concurrently in process with respect to the plurality of pipeline stages. The first circuit is configured to provide a first PC to a second pipeline stage of the plurality of pipeline stages. The first PC is derived from one of the plurality of PCs that corresponds to a first thread of the plurality of threads, and a first instruction entering the second pipeline stage is from the first thread.

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