Mini batch furnace

Electric heating – Heating devices – Combined with container – enclosure – or support for material...

Reexamination Certificate

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Details

C118S724000, C118S725000, C392S416000

Reexamination Certificate

active

06246031

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to semiconductor manufacturing equipment and, more particularly, to an apparatus, system, and method used for thermal processing of semiconductor wafers.
2. Description of the Related Art
During the processing of semiconductor devices, it is highly desirable to very accurately control the thermal treatment to which the devices are exposed during processing. In some instances, batches of devices, primarily wafers, are processed in a semiconductor processing furnace, which has a carefully controlled processing environment to effect the desired processes.
Of importance to the present invention are processing furnaces, which have vertically arranged wafer arrays and processing chambers. Vertically arranged furnaces were designed to provide better control of temperature and other processing parameters. For example, in U.S. Pat. No. 4,738,618, a vertically arranged thermal processor is disclosed having a vertically adjustable furnace assembly and process tube. The process tube, constructed from a quartz bell jar, is vertically moveable in up and down directions within a supporting framework in conjunction with a likewise moveable furnace assembly. Additionally, the furnace assembly and process tube are moveable together between up and down positions, as well as independently of one another. Heat is supplied to the thermal processor when the furnace assembly and process tube are both lowered into the down position by controlling operation of heating elements within the furnace assembly. To cool the process tube within the thermal processor, the operation of the heating elements is regulated, such that interior heat is dissipated to the exterior of the processor by convection.
It is generally desirable in vertically arranged furnaces to achieve a desired temperature environment within the process chamber so that wafers or other semiconductor devices are heated at uniform rates and to uniform temperatures. The more quickly the uniform environment is achieved the less risks of processing variations between wafers and between different batches of wafers. Unfortunately, it has been found that the desired temperature is usually non-uniform throughout the process chamber in all directions relative to the array of wafers being processed. The temperature non-uniformity is typically due to variations in temperature between different regions of the processing chamber. The ability to control these variations in temperature becomes more difficult as faster thermal ramp-up and ramp-down targets are attempted in the process chamber. In general, the conventional arrangement of heating elements used in and/or around the processing chamber creates a delay in thermal response of the process chamber temperature, which makes accurate dynamic control of the temperature during ramp-up, ramp-down, and changing temperature rate conditions particularly difficult.
For the above reasons, what is needed is an apparatus and method for isothermally distributing a temperature across the surface of a semiconductor device which provide an accurate dynamic control of the process temperature, without a degradation in uniformity of the processed wafers.
SUMMARY OF THE INVENTION
The present invention provides a heating apparatus, system, and method for isothermally distributing a temperature across a semiconductor device during processing. The present invention provides a furnace assembly, which includes a processing chamber. The processing chamber defines an internal cavity, which is configured to removably receive a wafer carrier or wafer boat, having a full compliment of semiconductor wafers. As described in greater detail below, a first heating circuit, including a plurality of resistive heating elements, is provided and advantageously arranged to surround the process chamber. A second heating circuit, which may also include a plurality of resistive heating elements, is provided and positioned proximate to the first plurality of heating elements. Preferably, in accordance with the present invention, the first heating circuit provides a variable temperature, which may be controlled during processing by varying the amount of energy emanating from each resistive heating element in response to a temperature fluctuation experienced within the process chamber. The second heating circuit provides a constant temperature distribution, which can be maintained during processing. In this manner, if a fluctuation in the process chamber temperature is sensed, the temperature of the first heating circuit can be adjusted to bring the process chamber temperature back to the constant and uniform heating temperature provided by the second heating circuit. Since the chamber is substantially kept at the desired processing temperatures by the second heating circuit, less energy is needed to adjust the temperature of the first heating circuit.
The wafer carrier is positioned vertically within the processing chamber using an actuation mechanism. After the wafers are processed, the actuation mechanism is used to remove the wafer carrier from the process chamber. The wafer carrier is transported to a cooling chamber, where the wafer cooling process may commence. Advantageously, as the wafer carrier is removed from the process chamber, the internal cavity is kept substantially enclosed using insulators, so that the processing temperature within the cavity can be substantially isothermally maintained. Accordingly, the risks of processing variations occurring between wafers and between different batches of wafers is substantially reduced in subsequent processing operations.
In one aspect of the present invention, a furnace assembly is provided for heating a plurality of substrates. The furnace assembly includes a furnace chamber, which has a process chamber mounted in space relation thereto. The process chamber is configured to receive the plurality of substrates. Also housed within the furnace assembly is a first heating circuit positioned proximate to the process chamber and a second heating circuit positioned proximate to the first heating circuit. A thermal energy output from the first heating circuit and the second heating circuit is capable of creating a substantially isothermal environment throughout the process chamber to heat each of the substrates.
In another aspect of the present invention, a system is provided for heating a plurality of substrates. The system includes a furnace assembly, which is configured to receive a plurality of substrates for processing. The system also includes a cooling chamber, which is configured to receive the plurality of substrates after processing. The furnace chamber remains substantially at a given temperature as the plurality of substrates are transported from a first position, within the furnace chamber and to a second position, within the cooling chamber.
In yet another aspect of the present invention, a method is provided for heating a plurality of substrates, which includes transporting said plurality of substrates to a first position within a process chamber; supplying a thermal energy output from a heat source to create a substantially isothermal environment within said process chamber; and transporting the plurality of substrates from said first position to a second position. The process chamber remains substantially isothermal during the transporting of the plurality of substrates from the first position to the second position.
The furnace assembly, system, and method of the present invention provide many other advantages. For example, since during continuous processing cycles the temperature of the process chamber does not substantially vary, less energy is required to maintain the process temperatures. The life usage of the heating elements is increased, since the heating circuits are not repeatedly ramping-up to load temperatures and ramping-down to cool. The present invention also makes it possible to process numerous wafer batches simultaneously, since while one batch is in the cooling phase of the ope

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