MIMD instruction flow computer architecture

Details MIMD instruction flow computer architecture MIMD instruction flow computer architecture

1988-08-15

1989-06-06

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

048376760

ABSTRACT:
A computer which achieves highly parallel execution of programs in instruction flow form, as distinguished from data flow form employing a unique computer architecture in which the individual units such as, process control units, programmable function units, memory units, etc., are individually coupled together by an interconnection network as self-contained units, logically equidistant from one another in the network, to be shared by any and all resources of the computer. All communications among the units now take place on the network. The result is a highly parallel and pipelined computer capable of executing instructions or operations at or approaching full clock rates.
Each process control unit initiates its assigned processes in sequence, routing the first instruction packet of each process through the network and addressed memories and function units back to the initiating process control unit where it is relinked with its process. As each instruction packet is routed, the initiating process is suspended until relinking occurs. Because the instruction flow computer is fully pipelined, the first instruction packet of the second process follows on the next machine cycle, and so on, until all of the processes have been initiated, providing time sharing of a single pipeline by multiple instruction packet streams.

REFERENCES:
patent: 3962706 (1976-06-01), Dennis et al.
patent: 3970994 (1976-07-01), Jenny
patent: 4012725 (1977-03-01), Spangler et al.
patent: 4075679 (1978-02-01), Christopher et al.
patent: 4128882 (1978-12-01), Dennis
patent: 4130885 (1978-12-01), Dennis
patent: 4145733 (1979-03-01), Misunas et al.
patent: 4149240 (1979-04-01), Misunas et al.
patent: 4153932 (1979-05-01), Dennis et al.
patent: 4201105 (1980-05-01), Alles
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4251861 (1981-02-01), Mago
patent: 4292666 (1981-09-01), Hill et al.
patent: 4365292 (1982-12-01), Barnes et al.
patent: 4412286 (1983-10-01), O'Dowd et al.
patent: 4418383 (1983-11-01), Doyle et al.
patent: 4437156 (1984-03-01), Christopher et al.
patent: 4450554 (1984-05-01), Steensma et al.
patent: 4466061 (1984-08-01), DeSantis et al.
patent: 4514807 (1985-04-01), Nogi
patent: 4542455 (1985-09-01), Demeure
patent: 4630258 (1986-12-01), McMillen et al.
The Hybrid Cube Network, R. J. McMillen et al.; Distributed Data Acquisition, Computing & Control Symposium; Dec. 1980, pp. 11-22.
Message-Switching Networks with Alternate Routing, U. Herzog; Proceedings of the International Teletraffic Congress, Stockholm, Jun. 13-20, 1973; Proc. 7, Part 2 Swedish Communications 173 (Stockholm, Sweden); pp. 415/1-415/8.
The Gamma Network: a Multiprocessor Interconnection Network Redundant Paths; D. S. Parker et al.: Conference Proceedings, The 9th Annual Symposium on Computer Architecture, Apr. 26-29, 1982; pp. 73-80.
Design and Implementation of the Banyan Interconnection Network in TRAC, U. V. Premkumar et al.; AFIPS 1980 National Computer Conference, Jun. 1980; pp. 643-653.
The Multistage Cube: a Versatile Interconnection Network, H. J. Siegel et al.; Computer, vol. 14, Dec. 1981; pp. 65-76.
Architecture and Applications of the HEP Multiprocessor Computer System, B. J. Smith; SPIE, vol. 298, Section on Real-Time Signal Processing IV, Aug. 1981; pp. 241-248.
Performance and Implementation of 4.times.4 Switching Nodes in an Interconnection Network for PASM, R. J. McMillen et al.; 1981 Int'l Conf. on Parallel Processing, Aug. 1981; pp. 229-233.
LSI Implementation of Modular Interconnection Networks for MIMD Machines, L. Ciaminiera et al.; 1980 Int'l. Conf. Parallel Processing, Aug. 1980, pp. 161-162.
Analysis and Simultation of Buffered Delta Networks, D. M. Dias et al.; IEEE Transactions on Computers, vol. C.30, No. 4; Apr. 1981; pp. 273-282.
A 4.times.4 Modular Crossbar Design for the Multistage Interconnection Networks, A. C. Hung et al.; Real Time Systems Symp., Dec. 1981; pp. 3-12.
Processor-Memory Interconnections for Multiprocessors, J. H. Patel; 6th Annual Int'l Symp. Computer Architecture, Apr. 1979; pp. 168, 177.
Switching Strategies in a Class of Packet Switching Networks, M. Kumar et al.; Conference Proceedings, The 10th Annual International Symposium on Computer Architecture, Stockholm, Sweden; 1983; pp. 284-300.
A Parallel Processor for Evaluation Studies, G. J. Nutt; Proceedings of the National Computer Conference, New York, Jun. 7-10, 1976; pp. 769-775.
The Polycyclic Processor, B. G. Chatterjee; IEEE International Conference on Computer Design: VLSI-Computers; 1983; pp. 84-87.
Multi-Microprocessor Based Architecture for Space Borne Packet Switch, P. N. Jean et al.; CONCOM 80, 20th IEEE Computer Society International Conference (San Francisco, U.S.); Feb. 25-28, 1980; pp. 139-142.
Programming Design Features of the Gama 60 Computer, P. Dreyfus; Proceedings, Eastern Joine Computer Conference 1958; pp. 174-181.
Chapter 13, a Multiple Instruction Stream Processor with Shared Resources, M. J. Flynn et al.; Parallel Processor Systems, Technologies, and Applications, Symposium, Jun. 25-27, 1969; pp. 251-286.

Affiliated with

Also associated with

Rating

MIMD instruction flow computer architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MIMD instruction flow computer architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MIMD instruction flow computer architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-44014