Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2000-10-25
2002-11-26
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S020000
Reexamination Certificate
active
06487651
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
The present invention relates generally to SIMD array processors, and more specifically to an SIMD array processor having a scalable and flexible architecture.
Single-Instruction Multiple-Data (SIMD) array processors are known which comprise multi-dimensional arrays of interconnected processing elements executing the same instruction simultaneously on a plurality of different data samples. For example, an SIMD array processor may include a two-dimensional array of processing elements in which each processing element is connected to its four (4) nearest neighbors to form a “North, East, West, South (NEWS) array”. In such NEWS arrays, each processing element communicates directly with its North, East, West, and South neighbors. The exemplary SIMD array processor may be incorporated in a processing system that includes a user computer interfaced with a processor controller that converts a given command sequence provided by the user computer to a corresponding instruction and broadcasts the instruction to the array of processing elements. An example of such a multi-dimensional processing system is disclosed in U.S. Pat. No. 5,193,202.
SIMD array processors can be used to solve a set of partial differential equations with associated boundary conditions that describe the nature of a physical environment over a finite volume of space. For example, a particular set of partial differential equations and boundary conditions may be approximated by a corresponding set of finite difference equations that describe values of dependent variables at a finite number of points or “nodes” distributed within a problem space. Further, after assigning a single processing element to each node and arranging the processing elements in the array so that each one can efficiently communicate with its nearest neighbors, the SIMD array processor can be used to calculate in parallel the dependent variable values at the finite number of nodes within the problem space.
One drawback of using SIMD array processors to solve such sets of finite difference equations is that the actual number of processing elements included in the SIMD array processor is often significantly less than the number of nodes required to solve the set finite difference equations. The above-mentioned multi-dimensional processing system of U.S. Pat. No. 5,193,202 addresses this problem by providing a virtual processing address and instruction generator that enables each processing element of an SIMD array processor to handle the processing for more than one node in a problem space.
Nevertheless, it would be desirable to have an SIMD array processor with an architecture that can be easily scaled to include increasing numbers of active processing elements. Such an architecture for an SIMD array processor would not only be scalable but also flexible to facilitate mapping of a node mesh onto the array of processing elements.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a scalable and flexible architecture for an SIMD array processor is provided that includes an array of processing elements, at least one processor controller coupled to the array of processing elements, a system area network for interconnecting at least one user computer and the processor controllers, and a storage area network for interconnecting at least one storage device and the processor controllers. In one embodiment, the processor controllers are part of a device cluster. In a preferred embodiment, the system area network further interconnects at least one user computer and at least one computer that is not coupled to an array of processing elements. One or more user computers can communicate with the processor controllers coupled to the array of processing elements and the computers not coupled to an array to use different portions of the array and/or different processor controllers and computers to solve different problems simultaneously.
The array of processing elements preferably has a hierarchical structure comprising backplanes, printed circuit boards, application specific integrated circuits, and arrays of processing elements. The SIMD array architecture can be scaled by increasing the quantity of backplanes, printed circuit boards, application specific integrated circuits, and/or by increasing the size of the arrays of processing elements. Moreover, the SIMD array architecture can be flexibly modified to achieve arrays of processing elements with different aspect ratios by selectively accessing data paths interconnecting the processing elements.
Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.
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Jackson James H.
Kleeman Michael W.
Melhem Georges
Mohindra Sanjeev
Assabet Ventures
Coleman Eric
Weingarten Schurgin, Gagnebin & Lebovici LLP
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