Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-03-27
2002-01-22
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S306000, C257S310000, C257S535000
Reexamination Certificate
active
06340832
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a Metal Insulator Metal (MIM) capacitor for a semiconductor integrated circuit device. More particularly, the present invention relates to such MIM capacitor and a method of manufacturing the same in which a capacitance error and phase rotation in a high frequency can be reduced.
BACKGROUND OF THE INVENTION
Conventionally, as a capacitor for a semiconductor integrated circuit device, there is known a Metal Oxide Semiconductor (MOS) capacitor. The MOS capacitor is manufactured as follows. First, a diffusion layer is formed in a semiconductor substrate which layer is also used as a lower electrode of the capacitor. Then, a dielectric layer is deposited on the diffusion layer and patterned. An upper electrode is then formed on the dielectric layer, and an oxide layer is formed on whole area of the semiconductor substrate. Thereafter, rectangular shaped openings for contacting the upper and lower electrodes are formed in predetermined locations of the oxide layer. A metal film made of aluminum and the like is formed on the oxide layer such that the openings are filled with the material of the metal film, and the metal film is then patterned. In this way, the conventional MOS capacitor is fabricated.
In the conventional MOS capacitor, when a high frequency signal is applied to it, a relatively large phase rotation occurs due to internal resistance of the MOS capacitor and, thereby, admittance is decreased. In Japanese patent laid-open publication No. 58-159367, comb-shaped capacitor contacts are used to avoid such disadvantage.
However, in the MOS capacitor disclosed in Japanese patent laid-open publication No. 58-159367, although the capacitor contacts each having a comb shape are used, a way of contacting the capacitor electrodes and an effective width of the capacitor are not optimized. Therefore, even in this capacitor, when a high frequency signal is applied thereto, an admittance of the capacitor is decreased.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to obviate the disadvantages of the conventional MIM capacitor for a semiconductor integrated circuit device.
It is another object of the present invention to provide an MIM capacitor for a semiconductor integrated circuit device in which admittance reduction when a high frequency signal is applied to the capacitor can be suppressed.
It is still another object of the present invention to provide an MIM capacitor for a semiconductor integrated circuit device in which parasitic resistance of the capacitor can be decreased.
It is still another object of the present invention to provide an MIM capacitor for a semiconductor integrated circuit device in which a way of contacting the electrodes of the capacitor and a width of the capacitor are optimized.
It is still another object of the present invention to provide an MIM capacitor for a semiconductor integrated circuit device in which capacitance error and phase rotation in a high frequency can be reduced.
It is still another object of the present invention to provide an MIM capacitor for a semiconductor integrated circuit device in which circuit characteristics of the semiconductor integrated circuit device can be improved.
According to an aspect of the present invention, there is provided an MIM capacitor for a semiconductor integrated circuit device comprising: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a lower electrode formed on the first insulating film; a second insulating film formed on the lower electrode; a first opening which penetrates the second insulating film and which reaches the lower electrode; a capacitor insulating film formed on a portion of the lower electrode exposed by the first opening; an upper electrode formed on the capacitor insulating film; a third insulating film formed on the second insulating film and the upper electrode; a second opening which penetrates the second and third insulating films and which reaches the lower electrode; a first lead electrode which fills the second opening, which connects to a portion of the lower electrode exposed via the second opening, and which is drawn out onto the surface of the third insulating film; a third opening which penetrates the third insulating films and which reaches the upper electrode; and a second lead electrode which fills the third opening, which connects to a portion of the upper electrode exposed via the third opening, and which is drawn out onto the surface of the third insulating film; wherein first lead electrode is continuously formed such that the first electrode surrounds at least three sides of the capacitor insulating film, and the width of the capacitor insulating film satisfies the following formula:
H<(A/F)
½
where, H designates the width of the capacitor insulating film, A designates a predetermined constant determined depending on a structure and a manufacturing process of the MIM capacitor to obtain desired admittance characteristics, and F designates maximum frequency of a signal used by the MIM capacitor.
In this case, it is preferable that the first lead electrode is a U-shaped electrode.
It is also preferable that the first lead electrode is a comb-shaped electrode.
It is further preferable that the first lead electrode is continuously formed such that the first lead electrode surrounds all sides of the capacitor insulating film.
It is advantageous that the capacitor insulating film is made of a material selected from a group consisting of silicon oxide, silicon oxynitride and silicon nitride.
It is also advantageous that the capacitor insulating film is made of a high dielectric constant material.
It is further advantageous that the capacitor insulating film is made of a material selected from a group consisting of
PbZr
1−x
Ti
x
O
3
(0≦x≦1), Pb
1−x
La
x
Zr
1−y
Ti
y
O
3
(0≦x≦1,0≦y≦1),
BaTiO
3
, Ba
1−x
Sr
x
TiO
3
(0≦x≦1), and SrTiO
3
.
It is preferable that the lower electrode and the upper electrode are made of polysilicon.
It is also preferable that the first and second lead electrodes are made of a material selected from a group consisting of aluminum, copper and gold.
It is further preferable that the first and second insulating films are made of silicon oxide, and the third insulating film is made of tetraethoxyorthosilicate.
According to another aspect of the present invention, there is provided a method of manufacturing an MIM capacitor for a semiconductor integrated circuit device comprising: preparing a semiconductor substrate; forming a first insulating film on the semiconductor substrate; forming a lower electrode on the first insulating film; forming a second insulating film on the lower electrode; forming a first opening by selectively removing the second insulating film, a portion of the lower electrode is exposed via the first opening; forming a capacitor insulating film on the portion of the lower electrode exposed by the first opening; forming an upper electrode on the capacitor insulating film; forming a third insulating film on the second insulating film and the upper electrode; forming a second opening by selectively removing the second and third insulating films, a portion of the lower electrode is exposed via the second opening; forming a third opening by selectively removing the third insulating film, a portion of the upper electrode is exposed via the third opening; forming a first lead electrode which fills the second opening, which connects to the portion of the lower electrode exposed via the second opening, and which is drawn out onto the surface of the third insulating film; and forming a second lead electrode which fills the third opening, which connects to the portion of the upper electrode exposed via the third opening, and which is drawn out onto the surface of the third insulating film; wherein, in the forming a second opening by selectively removing the second and third insulating films, the second opening is continuously formed such that the
Foley & Lardner
Munson Gene M.
NEC Corporation
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