Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-12-19
2003-07-29
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06600299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to voltage regulators, and more particularly to a Miller compensated NMOS low drop-out (LDO) voltage regulator using an inverting variable gain stage to improve stability and optimize power supply rejection ratio (PSRR).
2. Description of the Prior Art
Active compensating capacitive multiplier structures and techniques, e.g. nested Miller compensation, are well known in the art. The specific type of compensating circuit used is dependent upon the particular application. One application of improving phase margin for example, takes advantage of the Miller Effect by adding a Miller compensation capacitance in parallel with an inverting gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert g. Meyer,
Analysis and Design of Analog Integrated Circuits
, Third Ed., John Wiley & sons, Inc. New York, 1993, Ch. 9, especially pp. 607-623.
A typical architecture of a Miller compensated NMOS LDO voltage regulator
100
is shown in FIG.
1
. The LDO
100
comprises an error amplifier A
1
, an inverting inter-stage gain amplifier A
2
, a low impedance driver BUF, a NMOS power transistor NSW, feedback resistors R
1
and R
2
, and an output filter capacitor C_FILT with equivalent series resistor (ESR) R_ESR. It can be seen that the inverting inter-stage gain amplifier A
2
and the low impedance driver BUF get their supply from a charge pump
102
, that allows the gate of the NMOS power transistor NSW to be pulled up much higher than its drain, thus broadening the input range of the LDO
100
. It can be appreciated that the charge pump
102
is generally shared by multiple NMOS LDO's.
Similar to PMOS LDO's, the ultra-wide range of load current Iout
104
(usually from 10's &mgr;A to 100's mA) and the large output filter capacitor C_FILT (1 &mgr;F to 10 &mgr;F) also present significant challenges associated with compensation design for NMOS LDO's. The LDO
100
depicted in
FIG. 1
, for example, will very likely remain unstable if no special effort is taken to stabilize the Miller compensation loop. An analysis of the LDO
100
demonstrates the inter-stage gain amplifier A
2
serves a critical function to split the poles. Amplifier A
2
is expected to have high enough gain under low current conditions to push the second pole close or beyond unity gain bandwidth of the LDO. This high gain can be problematic however, under high load conditions where the second pole may be pushed up to a few MHz. Since this second pole is also the unity gain bandwidth of the Miller compensation loop itself, this huge bandwidth nearly always guarantees this loop is unstable, given the multiple stages inside the loop which all contribute to phase shift, albeit at a fairly high frequency range. Since the LDO
100
is a 4-pole system, the unity gain bandwidth must be close to or less than the second highest pole, or the system
100
will become unstable.
In view of the foregoing, a need exists for an LDO amplifier circuit architecture and technique capable of achieving better stability and higher PSRR performance from an internally compensated NMOS low drop-out voltage regulator than that presently achievable using conventional “Miller” or “Pole-splitting” techniques presently known in the art.
SUMMARY OF THE INVENTION
The present invention is directed to a circuit architecture and technique for achieving good phase margin, highly desirable open-loop gain, and high power supply ripple rejection (PSRR) from an internally compensated NMOS low drop-out voltage regulator that is implemented to formulate a modified type of Miller compensation. This good phase margin and high open-loop gain is achieved by using an inverting variable gain stage that ensures the dominant pole is always at the same internal node regardless of load current (no “pole swapping” allowed). The present circuit further provides high PSRR by implementing the inverting variable gain single stage amplifier such that a differential input has one input tied to C
c
while the other is at a dc voltage referenced to ground. Properly setting the input reference improves the PSRR.
A conventional NMOS low drop-out voltage regulator is generally comprised of two gain stages in order to promote simplification of any related compensated closed loop system. The input stage of such a voltage regulator is formulated via a differential amplifier. The output stage comprises a series pass NMOS device. These two stages are generally coupled together via an impedance buffer, typically a source follower, to enable the input stage high impedance output to drive the large gate capacitance of the series pass NMOS device and thereby minimize the effect of an internal pole that would otherwise interfere with loop compensation. Miller capacitor multiplication, or “Pole-splitting”, is generally used by those skilled in the art to internally compensate the voltage regulator for use with ceramic output capacitors where the circuit designer cannot rely on an external compensating zero formed by the ESR associated with an electrolytic capacitor. Generally, the Miller capacitor is tied across an inverting amplifier, a buffer and the NMOS pass device. It should be noted that the Miller capacitor will shunt the input stage amplifier output (also the inverting input of the inverting amplifier) to ground through a filter capacitor at high frequency, thus reducing the sensitivity of the inverting amplifier output to the supply noise; while the second input of the inverting amplifier is most preferably a voltage referenced to ground. This will help the gate of the NMOS pass device better reject supply noise, and hence improve the PSRR. In view of the foregoing, the present invention provides a low drop-out (LDO) architecture that employs an inverting variable gain stage to improve the internal compensation and achieve high PSRR performance from an internally compensated NMOS LDO voltage regulator.
A preferred embodiment of the present invention comprises a differential amplifier input stage, a variable gain, inversion, single stage differential amplifier second stage, and an output stage comprising a series pass NMOS device. The second and output stages are coupled together via an impedance buffer (e.g., source follower, or unity-gain feedback amplifier) to enable the input stage high impedance output to drive the large gate capacitance of the series pass NMOS device and thereby minimize the effect of an internal pole that would otherwise interfere with loop compensation. The inversion, variable gain differential amplifier stage has one input tied to C
c
and the other tied to a dc voltage referenced to ground. The Miller capacitance is then tied across multiple stages, i.e. the variable gain stage, the buffer, and the power NMOS.
A feature of the present invention is associated with a higher frequency pole at the filter capacitor achieved through partitioning the LDO into a two stage amplifier and using Miller capacitance for the compensation wherein the G
m
of the power NMOS is boosted at low load current and cut down at high load current using a wide band inversion, variable gain stage.
Another feature of the present invention is associated with better PSRR at high frequency by referencing the second input of the variable gain stage to ground thus minimizing the sensitivity of its output to supply noise.
Yet another feature of the present invention is associated with a flexible internally compensated NMOS low drop-out voltage regulator capable of functioning with a wide range of output capacitors and ESR values.
Still another feature of the present invention is associated with providing an internally compensated NMOS low drop-out (LDO) v
Brady III W. James
Kempler William B.
Riley Shawn
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