Patent
1992-11-04
1994-11-22
Shaw, Dale M.
G06F 1300
Patent
active
053676416
ABSTRACT:
An integrated circuit ("IC") interfaces a piece of communications equipment to a MIL-STD-1553 bus in accordance with the MIL-STD-1553 interface standards and operates in the MIL-STD-1553 defined bus controller mode of operation. The IC implements a command block configuration of data storage locations in an external memory. The command block includes a plurality of words arranged contiguously, a first word indicative of one of a plurality of different opcodes that define operation of the IC. The command block words include a MIL-STD-1553 defined command to be transmitted on the bus by the IC. A plurality of command blocks are arranged contiguously in a minor frame format. In order to sequentially execute a plurality of minor frames at different frequencies, the IC contains an internal timer that controls execution time of each minor frame. The first command block of each minor frame contains an opcode that loads the timer with a predetermined value for the corresponding frequency of execution of the particular minor frame. The timer counts down and decrements to zero before it is loaded with a value for execution frequency of the next minor frame. While the timer is decrementing, the IC executes the command blocks that follow the first command block.
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Carr Gregory S.
Hornback Timothy D.
Jordan Anthony F.
Pressprich John W.
Faller Fran R.
Kosakowski Richard H.
Shaw Dale M.
United Technologies Corporation
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