Mid-size NVM cell and array utilizing gated diode for low...

Details Mid-size NVM cell and array utilizing gated diode for low... Mid-size NVM cell and array utilizing gated diode for low...

2009-08-12

2010-12-28

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185180, C365S072000

Reexamination Certificate

active

07859912

ABSTRACT:
A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided.

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patent: 2007/0004119 (2007-01-01), Chun
patent: 2010/0157669 (2010-06-01), Audzeyeu et al.

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