Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-02-06
2002-11-05
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S275000, C257S280000, C257S472000, C257S473000
Reexamination Certificate
active
06476427
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority application No.2000-30818 filed on Feb. 8, 2000, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a high-speed semiconductor device having a low-resistance self-aligned gate electrode and a fabrication process thereof.
Compound semiconductor devices are semiconductor devices that use a compound semiconductor material such as GaAs for a channel region thereof. Thus, compound semiconductor devices have excellent high-frequency operational characteristics and are used extensively for high frequency or ultrahigh-frequency amplifiers in various electronic apparatuses including cellular phones in the form of MMIC (microwave monolithic integrated circuit), in which the compound semiconductor devices are integrated together with analog passive devices.
Generally, a compound semiconductor device for an MMIC uses a gate electrode of a refractory metal or a conductive compound such as silicide, and a pair of diffusion regions of n
+
-type are formed in a compound semiconductor substrate, on which the compound semiconductor device is constructed, in a self-alignment process such that the n
+
-type diffusion regions are formed at both lateral sides of the gate electrode. In such a self-alignment process, the n
+
-type diffusion regions are formed by an ion implantation process while using the gate electrode as a self-alignment mask. An example of such a compound semiconductor device is a MESFET.
In such a self-aligned MESFET, it is possible to avoid the problem of degradation of the Schottky contact right underneath the gate electrode, which may be caused at the time of the thermal annealing process conducted typically at the temperature of about 800° C. for activating the impurity elements introduced by the foregoing ion implantation process, by using a refractory conductive compound such as WSi for the gate electrode.
In view of the fact that such refractive conductive compounds have a resistivity larger than the resistivity of Au or Al, which is used commonly for a gate electrode of an ordinary MESFET, the gate electrode of the MESFET for use in such high-speed or microwave applications is generally formed to have a dual-layer structure in which a low-resistance metal electrode of W or Au is provided on the gate electrode of the refractory conductive compound for maximizing the operational speed.
Further, such a MESFET for microwave applications includes an ohmic electrode having a structure of Au/Ni/AuGe on the n
+
-type diffusion regions, wherein it should be noted that the AuGe component in the ohmic electrode forms an alloy at the interface to the GaAs substrate, and hence the desired ohmic contact.
In the case of analog circuits for ultra high-frequency applications, particularly an analog circuit for use in the final stage amplifier of a cellular phone, it is advantageous to integrate the compound semiconductor device on a compound semiconductor substrate together with other passive devices such as capacitors or inductances in the form of MMIC. By doing so, it becomes possible to eliminate the use of long interconnection wires and associated problems of parasitic capacitance and inductance. Thus, the construction of MMIC is thought advantageous for high-performance high-speed semiconductor devices.
FIGS. 1A-1E
show a conventional process of forming an MMIC including a self-aligned MESFET therein.
Referring to
FIG. 1A
, a buried p-type layer
11
A is formed in a semi-insulating GaAs substrate
11
in correspondence to the device region in which a self-aligned MESFET is to be formed, and a channel layer
11
B of n-type is formed on the buried p-type layer with an impurity concentration level adjusted such that the MESFET to be formed has a desired threshold characteristic.
In the step of
FIG. 1A
, a gate electrode
12
A of WSi is formed on the channel layer
11
B and a low-resistance gate electrode
12
B of W is formed on the gate electrode
12
A. The WSi gate electrode
12
A and the W gate electrode
12
B form together a single gate electrode structure
12
.
Next, in the step of
FIG. 1B
, an ion implantation process of an n-type impurity element is conducted while using the gate electrode structure
12
as a mask, and there are formed diffusion regions
11
C and
11
D of n
+
-type in the p-type buried layer
11
A at both lateral sides of the gate electrode structure
12
after conducting a thermal annealing process.
Next, in the step of
FIG. 1C
, ohmic electrodes
13
A and
13
B having the Au/Ni/AuGe structure are formed on the GaAs substrate
11
respectively in ohmic contact with the diffusion regions
11
C and
11
D, and a passivation film
14
and an interlayer insulation film
15
are deposited consecutively on the structure of FIG.
1
C.
Next, in the step of
FIG. 1D
, a contact hole
15
A is formed in the interlayer insulation film
15
so as to penetrate through the passivation layer
14
and expose the ohmic electrode
13
B, and a interconnection pattern
16
A is formed on the interlayer insulation film
15
in correspondence to the contact hole
15
A and an interconnection pattern
16
A is formed on the interlayer insulation film
15
in correspondence to the contact hole
15
A in electric contact with the ohmic electrode
13
B.
In the step of
FIG. 1D
, another interconnection pattern
16
B is formed on the interlayer insulation film
15
simultaneously to the interconnection pattern
16
A, and the interconnection patterns
16
A and
16
B are covered by a dielectric film
17
of SiN, and the like, in the step of FIG.
1
E. Further, an interlayer insulation film
18
is deposited in the step of
FIG. 1F
on the structure of FIG.
1
E. Further, an opening
18
A is formed in the interlayer insulation film
18
in correspondence to the electrode pattern
16
B, and an electrode pattern
19
is formed on the interlayer insulation film
17
in correspondence to the foregoing opening
18
A. Thereby, the electrode pattern
19
forms, together with the electrode pattern
16
B and the dielectric film
17
, a monolithic capacitor integral with the self-aligned MESFET.
The MMIC of
FIG. 1F
, while having the advantageous feature of integrating active devices operable in the ultra high-frequency band with a cooperating passive element, has a drawback in that it requires two interlayer insulation films, the layers
15
and
18
, and three interconnection pattern layers, the first interconnection pattern layer including the ohmic electrodes
13
A and
13
B, the second interconnection pattern layer including the interconnection patterns
16
A and
16
B, and the third interconnection layer including the electrode pattern
19
, and the fabrication process becomes inevitably complicated.
Further, the MMIC of
FIG. 1F
further has a drawback in that the use of a T-shaped gate structure for the gate electrode structure
12
for reducing the gate length of the lower gate electrode
12
A for further increase of the operational speed while simultaneously maintaining sufficient size for the upper low-resistance electrode
12
B for avoiding unwanted increase of gate resistance, is difficult. When such a T-shaped gate structure is used in the self-alignment process for forming the diffusion regions
11
C and lD, the upper low-resistance gate electrode
12
B acts as a mask and the diffusion regions
11
C and
11
D are formed with offset from the channel region right underneath the gate electrode
12
A. When such an offset is caused, there occurs the problem of increase of the source resistance and hence the problem of decrease of conductance of the MESFET.
In the MMIC of
FIG. 1F
, it should be noted that the electrode pattern
16
B forming the lower electrode of the capacitor is formed on the interlayer insulation film
15
, due to the circumstances that the semi-insulating GaAs substrate
11
in fact has a weak n-type conductivity. Thus, in t
Armstrong Westerman & Hattori, LLP
Fujitsu Quantum Devices Limited
Lindsay Walter
Niebling John F.
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