Microprogrammable devices using transparent latch

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G06F 922

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active

047915510

ABSTRACT:
In a microprogammed controller, the conventional pipeline register is replaced by a pair of coupled latches: a so-called "transparent" latch is placed between the output of the microprogram memory and the input of one or more system resources including at least the sequencer or address generator, and another latch is placed between the output of each such resource and the destination of its output. The appropriate bits of a microinstruction are supplied from the microinstruction memory to the associated resource via the transparent latch. The clock signal for the sequencer or other resource serves as the enable signal for the output latch (which can be either a transparent latch or an edge-triggered latch resposive to the rising edge of the clock signal), while the inverted sense of the clock signal provides the enable signal for the transparent latch. This allows data to propagate through the resource to internal destinations therein even before the results of the previous instruction are cleared from the resource's output latch. Set-up conditions for an instruction thus can occur within a resource while the results of the previious instruction are still sitting in the resource's output latch. Therefore those set-up conditions can already have been completed (or at least partially completed) before the results of the prior instruction are cleared out of the output latch and the new microinstruction is latched into the input latch.

REFERENCES:
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patent: 4450525 (1984-05-01), Demuth et al.
Microcomputer Interfacing, Artwick Bruce A., p. 147.
Computer System Architecture, Mano M. Morris, p. 22-23.
Digital Logic and Computer Design, Mano M. Morris, p. 258.
Lab Manual for ECE554 at the University of Wilson-Madison, Chapter II; Microprogrammed Design, FIG. 10, 12e, 12g AMD Databook, 1980-1981, pp. 2-147, FIG. D.
Electronics International, vol. 51, No. 23, 11-9-78, New York (US) Thomas M. Hedges, "Replacing Hardwired Logic with Microcode", for pages see International Search Report.
IBM Technical Disclosure Bulletin, vol. 22, No. 10, 3/80, NY (US), P. E. Anderson et al, "Two Speed Control Storage", pp. 4690-4691.

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