Boots – shoes – and leggings
Patent
1980-08-13
1984-01-31
Wise, Edward J.
Boots, shoes, and leggings
371 19, 364200, G06F 922, G06F 1100
Patent
active
044293682
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a microprogram-testing apparatus which can efficiently test a microprogram being newly developed for a microprogram controlled computer.
BACKGROUND ART
With a microprogram controlled computer, it is generally unnecessary to rewrite the contents of a microprogram memory after storing a microprogram. Where, therefore, a test is going to be made of a newly developed microprogram, the conventional process comprises writing a microprogram directly in a read only memory and mounting said read only memory on a microprogram memory section (MROM) 12. A cicroaddress control section (MAC) 11 is connected to the MROM 121 to provide an address of a location of the MROM 12 wherein a microinstruction to be read out is stored. A microinstruction register (MIR) 13 is connected to the MROM 12 to hold the microinstruction thus read out.
However, the above-mentioned arrangement has the drawbacks that it is necessary to write a microprogram in a fresh memory, each time the contents of a previously prepared microprogram are amended, consuming a considerable length of time; and a memory in which data is once stored fails to allow for the rewriting of any data therein, and is unavoidably thrown away, resulting an increase in a test cost. Therefore, attempts have been made to apply, for example, a programmable read only memory (PROM) capable of rewriting of data. However, such attempts are also accompanied with the difficulties that it takes much time to write data in such a memory; and the access time of said memory is so slow that clock pulses used throughout a combination of a computer and test apparatus (hereinafter referred to as a system) must have a low frequency, with the resultant failure to test the characteristic of said memory with the real time.
To resolve the above-mentioned problems, attempts have been made to replace a read only memory (ROM) by a random access memory which has a relatively fast access time and allows for both reading and writing. Application of such a memory indeed makes it possible to freely rewrite the contents of a microprogram. And also the microprogram test with the real time can be made using such a memory. However, said RAM renders its contents subject to destruction by, for example, noises or drift of power source voltage. Where therefore, a microprogram is tested while being stored in such memory, and a prescribed control fails, then difficulties arise in judging whether said failure results from the errors of the microprogram itself or the destruction of the contents of the memory.
Proposals advanced for solution of the above-mentioned problems include a data-processing apparatus set forth in, for example, the Japanese patent disclosure 142,939 (1976). This apparatus comprises a control memory in which microinstructions are stored and a control memory address register holding address data to have an access to said control memory. With this apparatus, a plurality of address data paired with control code data are successively read out of an address-storing device. Comparison is made between said address data and the contents of the control memory address register in a comparator. Where a coincidence output is delivered from the comparator, the address-storing device is accessed to read out the control data. An operation mode is controlled by the control data thus read out.
However, the data-processing apparatus described in the above-mentioned Japanese patent disclosure 142,939 (1976) in which address data are successively read out of the address-storing device lacks a function of halting the execution of a microprogram at an optionally chosen address to read out the contents of a general register and main memory.
Further, the Japanese patent disclosure 2146 (1977) sets forth a debugging device for a small processor. This debugging device comprises a memory for temporary storage where a microprogram being tested is stored, an interface circuit connected to an input-output unit for the debugging device, a console and a console circuit which decod
REFERENCES:
patent: 3937938 (1976-02-01), Matthews
patent: 3987420 (1976-10-01), Badagnani
patent: 4118789 (1978-10-01), Casto et al.
patent: 4275441 (1981-06-01), Takeuchi
Tokyo Shibaura Denki Kabushiki Kaisha
Wise Edward J.
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