Microprocessor with two groups of internal buses

Details Microprocessor with two groups of internal buses Microprocessor with two groups of internal buses

1990-07-13

1995-01-03

Kulik, Paul V.

Boots, shoes, and leggings

395800, 395200, 3642328, 36496431, 364DIG2, G06F 1300

Patent

active

053793943

ABSTRACT:
A microprocessor has a CPU, cache memories including TLBs, an internal memory control section (IMC) for controlling the data access operation to the cache memories, an external bus controller for controlling the data input/output operation between external memories and the cache memories, a first group of internal buses for connecting the CPU, the cache memories and IMC, and for transferring logical addresses, logical data and data among the CPU and the cache memories, and a second group of internal buses for connecting the cache memories, IMC and the external bus controller, and for transferring data among the cache memories and the external memories. Each cache memory and IMC are connected to the first group of internal buses and to the second group of internal buses in parallel, and the IMC controls the use of the second group of internal buses, and the data input/output operation to the group of the internal memories.

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Goss "Motorola's 88000: Integration, Performances and Applications," IEEE Compcon 89, Spring Digest of Papers, pp. 20-26, (Feb. 1989).

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