Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
1998-06-12
2001-04-24
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S032000, C712S033000, C712S034000, C712S041000, C712S201000, C712S202000, C712S203000
Reexamination Certificate
active
06223275
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a RISC (Reduced Instruction Set Computer) type microprocessor.
2. Description of the Related Art
A RISC processor has a set of instructions that allows the number of calculations to become minimum. A pipeline process of the RISC processor allows all instructions to be executed in the same and short time period. The bit length of instructions of a 32-bit RISC processor is fixed to 32 bits. Thus, in the RISC processor, the bit length of instructions is fixed and the instructions are simplified. With inter-register operations, most instructions can be executed in one clock cycle and thereby the pipeline process can be easily performed.
In the conventional 32-bit RISC processor, the bit length of instructions is fixed to 32 bits. However, the code efficiency of instructions of 32-bit fixed length is not high. In a RISC processor having variable length instructions, the load applied to the decoding portion becomes large. In addition, it takes a long time to perform a pipeline process for variable length instructions. To solve this problem, a branch cache is required. Thus, the circuit scale becomes large. To solve such a problem, the applicant of the present invention has proposed a RISC processor having 16-bit fixed instructions for improving code efficiency.
A 32-bit RISC processor has an address space of 4 Gigabytes (Gbytes). In the RISC processor, when a logical address is converted into a physical address, for mapping the address to a space of 4 Gbytes, a 1p.x macro instruction is provided. Conventionally, the 1p.x macro instruction is performed by dividing an LPI instruction into four instructions. Thus, a long type (32 bit) register branch instruction requires five instructions for 10 bytes.
In other words, conventionally, an LPI (Load Position Immediate) instruction as shown in
FIGS. 17A and 17B
is used. The LPI instruction is composed of 16 bits as shown in FIG.
17
A. In the instruction LPI, the high order six bits represent an operation code. The next two-bits BP represent the position of the bit pattern as shown in FIG.
17
B. When the value of BP is “11”, it represents the highest position (HH). When the value of BP is “10”, it represents the next highest position (HL). When the value of BP is “01”, it represents the third highest position (LH). When the value of BP is “00”, it represents the lowest position (LL). As shown in
FIG. 17A
, the next eight bits represent an operand designated by the value of an immediate. Thus, in the long type register branch instruction, the instruction LPI is divided into four instructions each of which is composed of eight bits. Thus, at least five instructions are required as a long type register branch instruction.
OBJECTS AND SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a microprocessor that allows a register branch instruction to be shortened and thereby to improve code efficiency.
The present invention is a reduced instruction set microprocessor, comprising an instruction decoder for dividing a task of an instruction process into simple stages and decoding the task through a pipeline process, an arithmetic and logic unit for performing arithmetic operations, a register group, a high speed multiplication/division unit for performing multiplications and divisions at high speed, an interrupt controller for performing an interrupt process, and an instruction set for limiting the all address space into an upper address space and executing a long type register branch instruction.
The high speed multiplication/division unit performs multiplications and divisions independent from the arithmetic and logic unit. The register group is composed of a dedicated control register group and a general purpose register group. The general purpose register group includes an accumulator, a stack pointer, and an interrupt stack pointer.
The general purpose register group further includes coprocessor registers. The coprocessor registers include registers for allowing a branch instruction to be changed and thereby a plurality of instructions to be executed with the same operation code and registers for accomplishing a simple stack.
All the address space is 4 Gbytes. The bit length of the instruction set is fixed to 16 bits. The limited address space is 2 Megabytes (Mbytes).
Thus, according to the present invention, SLIL and SLIH instructions that allow the all address space to be limited to an upper address space are provided. With the SLIL and SLIH instructions, the address space is limited to the upper 2 Mbytes so as to execute a long type register branch instruction with three instructions.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
REFERENCES:
patent: 4530050 (1985-07-01), Fukunaga et al.
patent: 5420809 (1995-05-01), Read et al.
patent: 5420992 (1995-05-01), Killian et al.
patent: 5764939 (1998-06-01), Caulk et al.
patent: 5930523 (1999-07-01), Kawasaki et al.
Goto Masaru
Miyachi Hiroaki
Sakamoto Yukihiro
An Meng-Al T.
El-Hady Nabil
Kananen Ronald P.
Rader Fishman & Grauer
Sony Corporation
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