Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Reexamination Certificate
1999-04-14
2001-11-06
Pan, Daniel H. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
C712S228000, C712S210000, C711S145000, C711S156000, C711S214000, C709S241000
Reexamination Certificate
active
06314510
ABSTRACT:
The present invention relates generally to context switching in microprocessors when handling traps. In particular, it pertains to a microprocessor that has reduced context switching overhead for handling traps and a corresponding method for reducing the context switching overhead in a microprocessor.
BACKGROUND OF THE INVENTION
In a conventional microprocessor, the state of the microprocessor must be saved when changing context while handling a trap. A trap may occur due to an interrupt received by the microprocessor from an external device or an exception detected by the microprocessor. This change of context involves saving the operands stored by the working registers of the microprocessor to the main memory of the microprocessor. However, the context switching overhead required to accomplish this operation is large since it is time consuming and a large portion of the main memory is used.
Several solutions have been proposed to reduce the large context switching overhead in a microprocessor. Each of these solutions recognizes that, at the time of a context switch, some of the working registers of the microprocessor contain active operands (i.e., operands still needed by the instruction stream) while others contain inactive operands (i.e., operands no longer needed by the instruction stream). These solutions require tracking of the active operands so that they are saved to the main memory during the next context switch.
One solution is to provide the microprocessor with register windows for the working registers. However, this is a complicated and hardware intensive way to postpone saving of the active operands to main memory until absolutely necessary. Thus, the context switching overhead for this solution is extremely large.
A more efficient solution is to include a dirty bit register for each working register. When a particular working register is written to with a new operand, then the dirty bit stored by the corresponding dirty bit register is set to indicate that the working register is dirty (i.e., has been written to) and stores an active operand that needs to be saved to memory at the next context switch. When the next context switch does occur, the operand is saved to the main memory and the dirty bit is cleared (i.e., re-set).
The problem with this solution is that the operand may have become inactive well before the next context switch even though the dirty bit still indicates that the operand is active. The microprocessor will then needlessly store this inactive operand to the main memory at the next context switch. This may also be the case for many other operands stored by the working registers. Thus, a bottleneck is created in saving these operands at the next context switch. This makes the context switching overhead for this solution unnecessarily large.
SUMMARY OF THE INVENTION
In summary, the present invention comprises a microprocessor with reduced context switching overhead and a corresponding method. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.
The previous dirty bit stored by the selected dirty bit register may have indicated that at least one of the one or more corresponding working registers is dirty and stores an operand that is active and needs to be saved to memory at the next context switch. However, all of the operands stored by the one or more corresponding working registers may in fact be inactive. In this case, the context switching overhead in the microprocessor is reduced by storing the new dirty bit in the selected dirty bit register. This is due to the fact that none of the operands will be saved to memory at the next context switch.
REFERENCES:
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patent: 6145049 (2000-11-01), Wong
patent: 0517282A1 (1992-10-01), None
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“Technique For Reducing The Number Of Registers Saved At A Context Swap,” IBM Technical Disclosure Bulletin, vol. 33, No. 3A, Aug. 1, 1990, pp. 234-235.
Garner et al., “The Scalable Processor Architecture (SPARC),” Sun Microsystems, Inc., 1988 IEEE, pp. 278-283.
Rice Daniel S.
Saulsbury Ashley
Flehr Hohbach Test Albritton & Herbert LLP
Pan Daniel H.
Sun Microsystems Inc.
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