Microprocessor with power saving clock

Details Microprocessor with power saving clock Microprocessor with power saving clock

2007-07-10

2007-07-10

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

10787029

ABSTRACT:
A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.

REFERENCES:
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patent: 5764711 (1998-06-01), Jokura
patent: 5774511 (1998-06-01), Boerstler
patent: 6522183 (2003-02-01), Sumi
patent: 6614320 (2003-09-01), Sullam et al.
patent: 6675249 (2004-01-01), Shimoda et al.
patent: 6687320 (2004-02-01), Chiu et al.

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