Microprocessor with pipeline status integrity logic for handling

Details Microprocessor with pipeline status integrity logic for handling Microprocessor with pipeline status integrity logic for handling

1997-08-28

1999-03-16

Treat, William M.

395591, G06F 938

Patent

active

058840621

ABSTRACT:
A microprocessor (5) having an on-chip floating point unit (31) is disclosed. According to the disclosed embodiments, the floating-point unit (31) is arranged in pipelined fashion, and permits out-of-order execution of instructions in the event that an instruction generates an exception, such as an underflow condition. Writeback queue control circuitry (70) is provided, which includes a writeback queue buffer (74) and a multiplexer (72). The multiplexer (72) is under the control of writeback queue control logic (75), and selects either the state of the writeback bus (WB) or the contents of the writeback queue buffer (74) for application to router circuitry (54), and thus writeback to a register file (39). Upon detection of an exception, the state of the writeback bus (WB) is forwarded to the execution units (56, 58, 60) for exception handling according to microcode, with a portion of the floating-point pipeline being flushed. Other instructions may execute, however, with their results stored in writeback queue buffer (74) until completion of the reformatting of the result having the exception. The contents of the writeback queue buffer (74) may be forwarded to the router circuitry (54) for writeback, and the floating-point status word (FSW) updated, in program order. Any of the results stored in the writeback queue buffer (74) that cause an exception may similarly be handled by the microcode sequence.

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