Microprocessor with integrated CPU, RAM, timer, and bus arbiter

Details Microprocessor with integrated CPU, RAM, timer, and bus arbiter Microprocessor with integrated CPU, RAM, timer, and bus arbiter

1986-10-23

1988-10-11

Eng, David Y.

Boots, shoes, and leggings

G06F 1318

Patent

active

047775912

ABSTRACT:
A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

REFERENCES:
patent: 4010448 (1977-03-01), Bennett
patent: 4042972 (1977-08-01), Gruner et al.
patent: 4067059 (1978-01-01), Derchak
patent: 4112490 (1978-09-01), Pohlman et al.
patent: 4354228 (1982-10-01), Moore et al.
patent: 4493021 (1985-01-01), Agrawal et al.
patent: 4511959 (1985-04-01), Nicolas et al.

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