Microprocessor with dual-port cache memory for reducing penalty

Details Microprocessor with dual-port cache memory for reducing penalty Microprocessor with dual-port cache memory for reducing penalty

1994-12-09

1995-11-07

Whitfield, Michael A.

395460, 395473, G06F 1300, G06F 1314

Patent

active

054653444

ABSTRACT:
A microprocessor has a CPU, an address converter which converts a logical address to a physical address, first and second latches which are controlled by a control signal and store the physical addresses, and a dual port cache memory device. The dual port cache memory device has decoders which operate according to second parts of outputs of the latches, dual port memory arrays which can be independently accessed by outputs of the decoders, a comparator which compares a physical address output from the dual port memory array and a first part of an output of the first latch to determine if they are the same, and a second comparator which compares a physical address output from the dual port memory array and a first part of an output of the second latch to determine if they are the same. The microprocessor is configured to effectively utilize the two ports of the dual port memory array of the dual port cache memory device, significantly improving the operating speed of the overall system by reducing the occurrence of penalties when consecutive instructions operating the cache memory are executed.

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